The present invention relates to flash memory devices and, more particularly, to a read method in which cell information can be read more accurately even when a cell threshold voltage has been shifted due to a cell retention characteristic.
A NAND flash memory device includes memory cells whose sources and drains are connected in series to one bit line to form a string. The memory cell generally has a transistor structure in which a floating gate and a control gate are stacked. A memory cell array is directly formed within a N-type well or P-type well formed in a P-type substrate or N-type substrate. The drain side of a NAND cell string is connected to the bit line through a select gate, and the source side is also connected to a source line through a select gate. The control gates of memory cells in adjacent cell stings are consecutively connected in a row direction and become a word line.
An operation of the NAND flash memory device is described below. A data write operation is sequentially performed starting from a memory cell, which is furthermost from the bit line. A control gate of a selected memory cell is applied with a high voltage Vpp, a control gate and a select gate of a memory cell on the bit line side of the selected memory cell are applied with an intermediate potential, and a bit line is applied with 0V or an intermediate potential depending on the data. If the bit line is applied with 0V, a potential is created between the drain and gate of the selected memory cell, so that electrons are injected into the floating gate. Due to this, the threshold voltage of the selected memory cell is increased.
In recent years, in order to further improve the degree of integration of flash memory, much research has been done on a multi-bit cell capable of storing a plurality of data bits in one memory cell. This kind of a memory cell is referred to as a “Multi Level Cell (MLC)”. A memory cell of a single bit, corresponding to the MLC, is referred to as a “Single Level Cell (SLC)”.
The MLC generally has four or more threshold voltage distributions, and four or more data storage states corresponding to the threshold voltage distributions. The MLC in which 2-bit data bits can be programmed has four data storage states; [11], [10], [00] and [01]. The states correspond to the threshold voltage distributions of the MLC.
For example, assuming that threshold voltage distributions of a memory cell are −2.7V or less, 0.3V to 0.7V, 1.3V to 1.7V, and 2.3V to 2.7V, the state [11] corresponds to −2.7V or less, the state [10] corresponds to 0.3V to 0.7V, the state [00] corresponds to 1.3V to 1.7V, and the state [01] corresponds to 2.3V to 2.7V. In other words, if the threshold voltage of the MLC corresponds to one of the four threshold voltage distributions, 2-bit data information corresponding to one of the states [11], [10], [00] and [01] is stored in the MLC.
As described above, the MLC has threshold voltage distributions corresponding to the square of 2 with respect to the number of bits that can be stored. That is, a MLC capable of storing m bits has 2m cell voltage distributions.
The cell voltage of the cell voltage distributions of the MLC is shifted as the storage period increases. This is called a “data retention characteristic”. That is, while data is stored, and then read over a long period of time, the cell voltage is shifted, which may cause a read error.